`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/05/08 10:51:11
// Design Name: 
// Module Name: lite_alg
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module lite_alg (
    input wire clk,
    input wire rst_n,
//    input ready1,
//    input ready2,
//    input ready3,
//    input ready4,
//    input ready5,
    input wire valid_in,
    output wire valid_out1,
    output wire valid_out2,
    output wire valid_out3,
    output wire valid_out4,
    output wire valid_out5,
    input wire [128-1:0] data_in,
    output [128-1:0] data_out1,
    output [128-1:0] data_out2,
    output [120-1:0] data_out3,
    output [64-1:0] data_out4,
    output [64-1:0] data_out5
    );
    
    m_seq m_seq(
        .clk     (clk     ),            
        .rst_n   (rst_n   ),   
    //    .ready   (ready1),
        .valid_in (valid_in),
        .valid_out(valid_out1),         
        .data_in (data_in ),
        .data_out(data_out1) 
    );
    
    lite_fnym lite_fnym(
        .clk     (clk     ),            
        .rst_n   (rst_n   ), 
    //    .ready   (ready2),    
        .valid_in (valid_in),
        .valid_out(valid_out2),        
        .data    (data_in ),
        .data_o  (data_out2) 
    );
    
    m_LSB m_LSB(
        .clk     (clk     ),            
        .rst_n   (rst_n   ),  
    //    .ready   (ready3),
        .valid_in (valid_in),
        .valid_out(valid_out3),           
        .data_in (data_in ),
        .data_out(data_out3) 
    );
    
    parity_grouping parity_grouping(
        .clk     (clk     ),            
        .rst_n   (rst_n   ),  
    //    .ready   (ready4),  
        .valid_in (valid_in),
        .valid_out(valid_out4),         
        .data_in (data_in ),
        .data_out(data_out4) 
    );
    
    xor_chain xor_chain(
        .clk     (clk     ),            
        .rst_n   (rst_n   ), 
    //    .ready   (ready5), 
        .valid_in (valid_in),
        .valid_out(valid_out5),           
        .data_in (data_in ),
        .data_out(data_out5) 
    );
    
endmodule
